1. Field of the Invention
The present invention relates to a row decoder for a semiconductor memory device, and in particular to a row decoder for a semiconductor memory device which is capable of driving a word line driving unit and a word line of a semiconductor memory in accordance with a pre-decoded row address signal.
2. Description of the Conventional Art
As shown in FIG. 1, a conventional row decoder for a semiconductor memory device includes a decoding unit 10 which has a NAND-gate constituted by NMOS transistors N1, N2 and N3 connected in series with a ground voltage Vss. The NMOS transistors N1, N2 and N3 respectively receive at their gates row address signals DRAi, DRAj and DRAk, pre-decoded by an externally connected pre-decoding unit (not shown), for NANDing the row address signals to thereby decode the same. The row decoder also includes a latch unit 20, which is composed of (1) a PMOS transistor P1 and an NMOS transistor N4 connected in series between a boosted power supply voltage Vpp and the ground voltage Vss to constitute a CMOS inverter for inverting an output signal from the decoding unit 10, and (2) a PMOS transistor P2, the gate of which receives an output signal from the inverter, the source of which receives the power supply voltage Vpp, and the drain of which is connected, at a node n0, with an output terminal of the decoding unit 10. The PMOS transistor 12 performs a pull-up function. The row decoder also includes a reset unit 30 composed of an NMOS transistor N5, the drain of which is connected with an output terminal of the latch unit 20, the source of which receives the ground voltage Vss, and the gate of which receives a word line reset signal OWR. The reset unit 30 is for resetting an output signal from the row decoder.
The output terminal of the conventional row decoder is connected with a word line driver (not shown) for driving an associated word line WL of a memory.
The above-described row decoder is disclosed in U.S. Pat. No. 5,412,331. The operation thereof will now be explained.
First, in a state that the word line is not selected, the NMOS transistor N5 is turned on by a high level word line reset signal OWR, and the voltage at a connection node n1, connected with the latch unit 20 and the reset unit 30, is pulled-down to a low level of the ground voltage Vss, whereby an output signal of the row decoder supplied to a corresponding word line driver (not shown) maintains a low level reset state.
In addition, the pull-up PMOS transistor P2 of the latch unit 20, the gate of which receives the low level signal from the node n1, is turned on, and the voltage at the node n0 connected between the drain terminal of the PMOS transistor P2 and the output terminal of the decoding unit 10 becomes a high level, so that the NMOS transistor N4 of the latch unit 20 is turned on, whereby the output signal from the row decoder maintains a low level.
When the word line is selected, the word line reset signal OWR becomes a low level, and the NMOS transistor N5 of the reset unit 30, the gate of which receives the low level word line reset signal OWR, is thereby turned off. When the pre-decoded address signals DRAi, DRAj, and DRAk all become high, the NMOS transistors N1 through N3 are turned on to connect the node 0 to the ground voltage Vss so that the voltage on the node 0 is discharged and assumes the low level ground voltage Vss. Accordingly, the low level voltage is applied to the respective gates of the PMOS transistor P1 and the NMOS transistor N4 of the latch unit 20, which together operate as in inverter.
Thereafter, as the PMOS transistor P1 of the inverter is turned on, the output signal from the row decoder assumes a pulled-up state of a high level of the power voltage Vpp, and an external word line driver (not shown) is driven by the output signal from the row decoder, and the word line WL (not shown) connected with the external word line driver is activated so that data is read from or written to a memory cell (not shown).
At this time, the pull-up PMOS transistor P2 the gate of which receives the high level output signal from the latch unit 20 is turned off, and the node n0 signal, which supplies an input signal to the CMOS inverter composed of transistors P1 and N4, is influenced only by the pulled-down output voltage through the NMOS transistors N2, N3, and N4, which perform a NANDing operation of the pre-decoded address signals.
However, in the conventional row decoder, since the voltage level of the externally boosted voltage Vpp applied through the pull-up PMOS transistor P2 is higher than that of the pre-decoded row address signals DRAi, DRAj and DRAk which are inputted to the respective gates of the NMOS transistors N1, N2 and N3 of the decoding unit 10, when a word line is selected, the voltage at the node n0 connected with the decoding unit 10 and the latch unit 20 slowly transitions from a high level to a low level, the amount of current flowing through the NMOS transistors N1, N2, and N3 of the decoding unit 10 is increased, and the power consumption is thereby increased. In order to overcome the above-described problems, the NMOS transistors N1, N2 and N3 are made large so that the NMOS transistors N1, N2 and N3 of the decoding unit 10, which operates as a pull-down NAND-gate, operate more powerfully than the PMOS transistor P2 of the latch unit 20. But, in consequence the layout area of the semiconductor memory device is disadvantageously increased.